Differences Between ARM6 and Earlier ARM Processors
Table of Contents
The ARM6 series (ARM6, ARM60 and ARM600) is a family of ARM
processors which have 32-bit program counters. Earlier ARMs (ARM2, ARM3
and ARM2aS) had a 26-bit program counter (PC). This application note
describes the major differences between the two types of processor.
The introduction of the larger program counter has meant that the flags
and control bits which previously occupied the other bits of R15 (the
combined PC and PSR) have been moved to a separate register. The extra
space in the new register (the CPSR, Current Program Status Register)
allows for more control bits, and a further three mode bits have been
added to allow for a larger number of operating modes.
The removal of the PSR to a separate register also means that it is no
longer possible to save these flags automatically in R14 when a Branch
with Link instruction is executed or when an exception occurs. Program
analysis has shown that the saving of these flags is required in just 3%
of subroutine calls, so there is only a slight overhead in explicitly
saving them on a stack when necessary. To cope with the requirement of
saving them when an exception occurs, a further five registers have been
provided to hold a copy of the CPSR at the time of the exception. These
registers are the Saved Program Status Registers (SPSRs). There is one
SPSR for each of the modes that the processor may enter as a result of
the various types of exception.
The expansion of the PC to 32 bits also means that the Branch
instruction can no longer specify a branch to the entire program space,
and is now limited to +/- 32 Mbytes. Branches greater than +/- 32 Mbytes
can be made with other instructions, but the equivalent of the Branch
with Link instruction will require a separate instruction to save the PC
in R14.
There are a total of ten operating modes in two overlapping sets. Four
modes allow the processor to behave like the earlier ARM processors with
26-bit PC: User26, IRQ26, FIQ26 and Supervisor26, which correspond to
the four operating modes of the ARM2 and ARM3 processors. There are a
further four operating modes User32, IRQ32, FIQ32, Supervisor32 which
can be used when the process is running with the full 32bit PC.
The final two modes are Undefined32 and Abort32. These are entered when
the Undefined instruction and Abort exceptions occur.They have been
added to remove restrictions on Supervisor mode programs which exist
with the ARM2 and ARM3 processors. The two sets of User, FIQ, IRQ and
Supervisor modes each share a set of banked registers to allow them to
maintain some private state at all times. The Abort and Undefined modes
also have a pair of banked registers each for the same purpose.
The instruction set is changed in two major areas: the introduction of
new instructions and restrictions on the use of existing ones.
The new instructions allow access to the CPSR and SPSR registers. They
are formed by using opcodes from the data processing group of
instructions that were previously unused. Specifically, these are the
TST, TEQ, CMP and CMN instructions with the S flag clear. They are now
known as MSR which moves data into the CPSR and SPSR registers, and MRS
which moves from CPSR and SPSR to a general register. The data moved to
CPSR and SPSR can be either the contents of the general register or an
immediate value.
Certain limitations have been introduced on the use of ARM instructions.
In all cases, if these restrictions are not observed, the behaviour of
the processor is the same as that of the ARM2aS macrocell. However there
is no guarantee that future ARM processors will behave in the same way.
When configured for 32-bit program and data space, the ARM6 family
supports operation in 26-bit modes for compatibility with the ARM
processors that have a 26-bit address space. The 26-bit modes are
User26, FIQ26, IRQ26 and Supervisor26. When a 26-bit mode is selected,
the programmer's model reverts to that of existing 26-bit ARMs (ARM2,
ARM3, ARM2aS). The behaviour is that of the ARM2aS macrocell with the
following differences:
- Address exceptions are never generated. The OS may simulate the
behaviour of the address exceptions by using external logic such as a
memory management unit to generate an abort if the 64 Mbyte range is
exceeded, and convert that abort into an address exception trap for the
application.
Note that address exceptions are still possible when the processor is configured for 26-bit program and data space.
- The new instructions to transfer data between general registers
and program status registers remain operative. The new instructions can
be used by the operating system to return to a 32-bit operating mode
after calling a binary containing code that was written for a 26-bit
ARM.
- All exceptions (including Undefined Instruction and Software
Interrupt) return the processor to a 32-bit mode, so the operating
system must be modified to handle them.
- The ARM6 family includes hardware which prevents the write
operation and generates a data abort if the processor attempts to write
to a location between &00000000 and &0000001F inclusive (the
exception vectors) when operating in 26-bit mode. This allows the
operating system to intercept all changes to the exception vectors and
redirect the vector to some veneer code. The veneer code should place
the processor in a 26-bit mode before calling the 26-bit exception
handler.
In all other respects, the ARM6 family behaves like a 26-bit ARM when
operating in 26-bit mode. The relevant bits of the CPSR appear to be
incorporated back into R15 to form the PC/PSR with the I and F bits in
bits 27 and 26. The instruction set behaves like that of the ARM2aS
macrocell with the addition of the MRS and MSR instructions.
A program executing in a privileged 32-bit mode can enter 26-bit mode by
executing a MSR instruction that alters the mode bits to one of the
values shown below:
Table 1: CPSR Mode bit settings |
M[4:0] | Mode | Accessible registers |
00000 | USR26 | PC/PSR, R14...R0,CPSR |
00001 | FIQ26 | PC/PSR,R14_fiq...R8_fiq, R7...R0,CPSR,SPSR_fiq |
00010 | IRQ26 | PC/PSR,R14_irq...R13_irq, R12...R0,CPSR,SPSR_irq |
00011 | SVC26 | PC/PSR,R14_svc...R13_svc, R12...R0,CPSR,SPSR_svc |
Transfer between 26- and 32-bit mode happens automatically whenever an
exception occurs in 26-bit mode. Note that an exception (including
software interrupt) arising in 26-bit mode will enter 32-bit mode and
the saved value in R14 will contain only the PC, even though the PSR was
also considered part of R15 when the exception arose.
In addition, the MSR instruction provides the means for a program in a
privileged 26-bit mode to alter the mode bits to change to a 32-bit
mode.